On 14th March, Associate professor Toprasertpong Kasidit, Department of Electrical Engineering and Information Systems, and his team received 16th Silicon Technology Division Paper Award (The Japan Society of Applied Physics).
16th Silicon Technology Division Paper Award (The Japan Society of Applied Physics)
The Silicon Technology Division Paper Award recognizes original research papers of high academic value in the field of silicon technology. It is awarded to authors of papers published in academic journals within the past three years. Each year, only one or two papers in the silicon technology field are selected for this award.
About awarded research
Associate Professor Kasidit Toprasertpong, Kento Tahara (M2 at the time), Professor Mitsuru Takenaka, and Professor Shinichi Takagi of the Department of Electrical Engineering and Information Systems have been awarded the 16th Silicon Technology Division Paper Award (The Japan Society of Applied Physics) on March 14, 2025, in recognition of their outstanding research contributions to the field of silicon technology. The awarded paper is as follows:
Awarded Paper:
"Low operating voltage, improved breakdown tolerance, and high endurance in Hf0.5Zr0.5O2 ferroelectric capacitors achieved by thickness scaling down to 4 nm for embedded ferroelectric memory," ACS Applied Materials & Interfaces 14, pp. 51137-51148, Nov. 2022.
Authors: Kasidit Toprasertpong, Kento Tahara, Yukinobu Hikosaka, Ko Nakamura, Hitoshi Saito, Mitsuru Takenaka, Shinichi Takagi
Summary of the Paper:
This paper provides a comprehensive report on the technology for thinning HfZrO2 ferroelectric films, covering process requirements, operating voltage, reliability, and device demonstration. The study experimentally demonstrates that the high operating voltage and the dielectric breakdown, which are two critical challenges for embedded memory, can both be overcome by thickness down scaling. Furthermore, the relationship between film thickness and ferroelectric phase formation temperature was systematically investigated, leading to the construction of a thickness-temperature map, which is currently widely used in the hafnia ferroelectric community.
Based on these insights, the authors successfully demonstrated a ferroelectric memory with low process temperatures, sub-1-V operation, endurance exceeding 100 trillion cycles, and data retention exceeding ten years. These achievements open new directions in non-volatile memory technology and are expected to drive innovation in next-generation computing systems by enabling logic-integrated memory and 3D memory stacking.
Award website: https://annex.jsap.or.jp/silicon/awards/archive/award-2024
Your impression & future plan
In this study, we showed that thinning the ferroelectric film can achieve low-voltage operation and high reliability, and I believe this approach will become an important foundation for future logic-integrated memory and 3D integration. Following this award, I will continue to push forward with research toward next-generation semiconductor technologies and work on creating new device and system technologies based on ferroelectric materials.