New Architecture for Phase-Locked Loops Toward Next-Generation Communications: Achieving Low Jitter and Low Spurious Simultaneously Without Calibration

Next-generation wireless communication standards such as Beyond 5G and 6G demand not only ultra-high data rates but also low latency and high energy efficiency. To achieve high-speed communication within limited frequency resources, advanced modulation schemes such as 4K-QAM, adopted in standards like Wi-Fi 7, are increasingly employed. However, these high-order modulation schemes impose stringent requirements on signal quality, making ultra-low-noise and high-precision circuit technologies indispensable for wireless transceivers.

In wireless communication systems and radar, the phase-locked loop (PLL) is a key component that generates reference frequency signals, and its performance directly impacts overall communication quality. In particular, generating cleaner reference signals with low power consumption and short settling time is critical, as this improves system throughput and energy efficiency. Consequently, research and development of high-performance PLLs is actively pursued worldwide to enable next-generation wireless systems and high-precision radar.

A research group led by Professor Tetsuya Iizuka and graduate student Haoming Zhang at the Graduate School of Engineering, The University of Tokyo, has developed a novel PLL architecture that simultaneously achieves low jitter and low spurious without requiring calibration, with support from JST Cutting-edge Research and Development on Information & Communication Sciences (CRONOS) program.

Fractional-N PLLs, widely used in wireless devices, suffer from degraded noise performance due to quantization noise inherent in their architecture. Numerous techniques have been proposed to suppress this noise, but most existing approaches rely on circuit-level compensation, which increases lock time and hardware complexity. In this study, the team introduced a new cascaded PLL structure employing two multi-modulus dividers (MMDs) for quantization noise cancellation and a feed-forward noise cancellation technique to reduce oscillator noise in the first stage. This innovative design enables a low-noise fractional-N PLL without calibration.

The developed PLL was fabricated in a 65 nm CMOS process and demonstrated jitter performance of 157 fs and spurious performance of –73 dBc, maintaining stable, low-noise characteristics across output frequencies and division ratios. This technology is expected to serve as a critical low-noise frequency synthesizer for high-speed wireless communication, paving the way for Beyond 5G and 6G applications.

Block diagram of the newly developed phase-locked loop architecture.

Papers
Conference: International Solid-State Circuits Conference (ISSCC)
Title: A 157fs_rms-Jitter, −73dBc-Fractional-Spur, Calibration-Free Cascaded SPLL Employing Robust Feedforward Noise Cancellation and MMD-Based Quantization-Error Cancellation with a 60MHz Reference
Authors: Haoming Zhang, Yongjuan He, Yuyang Zhu, Huanyu Ren, and Tetsuya Iizuka*

URL: https://www.isscc.org/